Tool : SelfTest, 6.2.3.19967 Filename : C:\Program Files (x86)\Intel\SelfTest\DC\windump.st Date/Time: 28.07.2012 16:11:45 Stats : Total:26196 Error:27 Warn:378 ********************************************************************************* ********************************************************************************* CPU 0 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 1 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 2 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 3 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 4 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 5 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 6 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* CPU 7 BWG Version - Nehalem Processor Family BIOS Writer’s Guide (BWG) 0.7 Actual Expected --------------------------------------------------------------------------------- 1Bh IA32_APIC_BASE – XAPIC Base Register [10] APIC Extended Mode (R/W) 0x0 UNTESTED This bit field is not checked in this current tool version. Enable/disable for APIC extensions. 1= enabled, 0 = disabled Modes: Bit 11 Bit 10 Description 0 0 Disabled 0 1 Illegal - GP exception 1 0 Legacy xAPIC Mode (default) 1 1 Extended xAPIC Mode Note: Software must test the EXT xAPIC feature flag before attempting to set this bit. The EXT xAPIC feature flag is returned in ECX[21] after executing the CPUID instruction with EAX initially set to 1. A GP exception will be raised if software attempts to set this bit and the EXT xAPIC feature flag is not set. Note: A GP exception will be raised if the APIC Global Enable Bit (bit 11) is not set to a 1 when this bit is written to a 1. Note: Since it is not supported to transition from extended APIC mode to legacy APIC mode (bits[11:10] 11b -> 10b), GP exception will also be raised in some situations when this bit is written to 0. --------------------------------------------------------------------------------- E2h PMG_CST_CONFIG_CONTROL W [26] C1_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 Note: If processor signature (CPUID.(EAX=01h):EAX) >= 000106A2h, then this bit is defined as: C1_STATE_AUTO_DEMOTION_ENABLE (R/W) When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. W [25] C3_STATE_AUTO_DEMOTION_ENABLE 0x1 0x0 When set, processor will conditionally demote C6/C7 requests to C3 based on uncore autodemote information. W [15] CFG Lock. (R/WO) 0x0 0x1 When set, locks this bits [15:0] of this register for further writes until the next reset occurs. --------------------------------------------------------------------------------- 1AAh MISC_PWR_MGMT E [22] Lock TM Interrupt. (R/W) 0x0 0x1 Ties thermal monitor interrupts from all cores. If set then thermal interrupt on single core is routed to all cores. A value = 0 indicates not active, and a value = 1 indicates active. BIOS should set this bit to a 1. --------------------------------------------------------------------------------- 1FCh POWER_CTL W [1] C1E Enable 0x0 0x1 When set, will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep technology operating point when all execution cores enter MWAIT (C1). Frequency transition will switch immediately, followed by gradual Voltage switching. The CPU will switch back to the original operating point once any execution core exits to C0. --------------------------------------------------------------------------------- 26Ch MTRRFIX4K_E0000 W [63:56] E7000-E7FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] E6000-E6FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] E5000-E5FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] E4000-E4FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] E3000-E3FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] E2000-E2FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E1000-E1FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E0000-E0FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Dh A624 MTRRFIX4K_E8000 W [63:56] EF000-EFFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] EE000-EEFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] ED000-EDFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] EC000-ECFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] EB000-EBFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] EA000-EAFFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] E9000-E9FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] E8000-E8FFF 0x0 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Eh MTRRFIX4K_F0000 W [63:56] F7000-F7FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] F6000-F6FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] F5000-F5FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] F4000-F4FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] F3000-F3FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] F2000-F2FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F1000-F1FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F0000-F0FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 --------------------------------------------------------------------------------- 26Fh MTRRFIX4K_F8000 W [63:56] FF000-FFFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [55:48] FE000-FEFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [47:40] FD000-FDFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [39:32] FC000-FCFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [31:24] FB000-FBFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [23:16] FA000-FAFFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [15:8] F9000-F9FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 W [7:0] F8000-F8FFF 0x4 0x5 Uncacheable (UC) 0 Write Combining (WC) 1 Write-through (WT) 4 Write-protected (WP) 5 Writeback (WB) 6 Reserved Encodings 2, 3, 7 through 225 ********************************************************************************* Core IOH (Tylersburg) EDS Spec Version - 1.5 Bios Spec Version - 1.03 Bus: 0, Dev: 20, Func: 0 Actual Expected --------------------------------------------------------------------------------- Memory Mapped IO W BAR is disabled The BAR is disabled so no registers will be tested. Enable the BAR and collect a new dump file. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 26, Func: 0 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 26, Func: 1 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 26, Func: 2 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* EHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 26, Func: 7 Actual Expected --------------------------------------------------------------------------------- 6Ch USB EHCI Legacy Support Extended Control / Status W [31] SMI on BAR 0x1 0x0 Attribute: RWC Default: 0 Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written. 1 = This bit is set to 1 when the Base Address Register (BAR) is written. --------------------------------------------------------------------------------- FCh Reserved E [16:4] Reserved 0x130 0x170 ********************************************************************************* PCI Express* Root Port EDS Spec Version - 2.1 Bios Spec Version - 0.9 Bus: 0, Dev: 28, Func: 0 Actual Expected --------------------------------------------------------------------------------- 4Ch LINK CAPABILITIES REGISTER E [11:10] Active State Link PM Support (APMS) 0x1 0x3 Desktop platform 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/WO Indicates what level of active state link power management is supported on the root port. Bits\tDefinition 00b\tNeither L0s nor L1 are supported 01b\tL0s Entry Supported 10b\tL1 Entry Supported 11b\tBoth L0s and L1 Entry Supported --------------------------------------------------------------------------------- 50h LINK CONTROL REGISTER W [1:0] Active State Link PM Control (APMC) 0x0 1,3 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/W Default: 0 Indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s Entry Enabled 10 = Reserved 11 = L0s and L1 Entry Enabled --------------------------------------------------------------------------------- 52h LINK STATUS REGISTER W [13] Data Link Layer Active (DLLA) 0x1 0x0 Attribute: RO Default: 0 Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state --------------------------------------------------------------------------------- 70h Link Control 2 Register W [3:0] Target Link Speed (TLS) 0x0 0x1 Default: 0 This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b: 2.5 GT/s Target Link Speed All other values reserved --------------------------------------------------------------------------------- E1h Root Port Dynamic Clock Gating Enable W [3] Shared Resource Dynamic Link Clock Gating 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource link clock domain. 0 = Disables dynamic clock gating of the shared resource link clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [2] Shared Resource Dynamic Backbone Clock Ga 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource Backbone clock domain. 0 = Disables dynamic clock gating of the shared resource Backbone clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [1] Root Port Dynamic Link Clock Gate Enable 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port link clock domain. 0 = Disables dynamic clock gating of the root port link clock domain. W [0] Root Port Dynamic Backbone Clock Gate Ena 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port Backbone clock domain. 0 = Disables dynamic clock gating of the root port Backbone clock domain. ********************************************************************************* PCI Express* Root Port EDS Spec Version - 2.1 Bios Spec Version - 0.9 Bus: 0, Dev: 28, Func: 1 Actual Expected --------------------------------------------------------------------------------- 4Ch LINK CAPABILITIES REGISTER E [11:10] Active State Link PM Support (APMS) 0x1 0x3 Desktop platform 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/WO Indicates what level of active state link power management is supported on the root port. Bits\tDefinition 00b\tNeither L0s nor L1 are supported 01b\tL0s Entry Supported 10b\tL1 Entry Supported 11b\tBoth L0s and L1 Entry Supported --------------------------------------------------------------------------------- 50h LINK CONTROL REGISTER W [1:0] Active State Link PM Control (APMC) 0x0 1,3 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/W Default: 0 Indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s Entry Enabled 10 = Reserved 11 = L0s and L1 Entry Enabled --------------------------------------------------------------------------------- 52h LINK STATUS REGISTER W [13] Data Link Layer Active (DLLA) 0x1 0x0 Attribute: RO Default: 0 Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state --------------------------------------------------------------------------------- 70h Link Control 2 Register W [3:0] Target Link Speed (TLS) 0x0 0x1 Default: 0 This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b: 2.5 GT/s Target Link Speed All other values reserved --------------------------------------------------------------------------------- E1h Root Port Dynamic Clock Gating Enable W [3] Shared Resource Dynamic Link Clock Gating 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource link clock domain. 0 = Disables dynamic clock gating of the shared resource link clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [2] Shared Resource Dynamic Backbone Clock Ga 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource Backbone clock domain. 0 = Disables dynamic clock gating of the shared resource Backbone clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [1] Root Port Dynamic Link Clock Gate Enable 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port link clock domain. 0 = Disables dynamic clock gating of the root port link clock domain. W [0] Root Port Dynamic Backbone Clock Gate Ena 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port Backbone clock domain. 0 = Disables dynamic clock gating of the root port Backbone clock domain. ********************************************************************************* PCI Express* Root Port EDS Spec Version - 2.1 Bios Spec Version - 0.9 Bus: 0, Dev: 28, Func: 3 Actual Expected --------------------------------------------------------------------------------- 4Ch LINK CAPABILITIES REGISTER E [11:10] Active State Link PM Support (APMS) 0x1 0x3 Desktop platform 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/WO Indicates what level of active state link power management is supported on the root port. Bits\tDefinition 00b\tNeither L0s nor L1 are supported 01b\tL0s Entry Supported 10b\tL1 Entry Supported 11b\tBoth L0s and L1 Entry Supported --------------------------------------------------------------------------------- 50h LINK CONTROL REGISTER W [1:0] Active State Link PM Control (APMC) 0x0 1,3 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/W Default: 0 Indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s Entry Enabled 10 = Reserved 11 = L0s and L1 Entry Enabled --------------------------------------------------------------------------------- 52h LINK STATUS REGISTER W [13] Data Link Layer Active (DLLA) 0x1 0x0 Attribute: RO Default: 0 Default value is 0b. 0 = Data Link Control and Management State Machine is not in the DL_Active state 1 = Data Link Control and Management State Machine is in the DL_Active state --------------------------------------------------------------------------------- 70h Link Control 2 Register W [3:0] Target Link Speed (TLS) 0x0 0x1 Default: 0 This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b: 2.5 GT/s Target Link Speed All other values reserved --------------------------------------------------------------------------------- E1h Root Port Dynamic Clock Gating Enable W [3] Shared Resource Dynamic Link Clock Gating 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource link clock domain. 0 = Disables dynamic clock gating of the shared resource link clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [2] Shared Resource Dynamic Backbone Clock Ga 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource Backbone clock domain. 0 = Disables dynamic clock gating of the shared resource Backbone clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [1] Root Port Dynamic Link Clock Gate Enable 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port link clock domain. 0 = Disables dynamic clock gating of the root port link clock domain. W [0] Root Port Dynamic Backbone Clock Gate Ena 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port Backbone clock domain. 0 = Disables dynamic clock gating of the root port Backbone clock domain. ********************************************************************************* PCI Express* Root Port EDS Spec Version - 2.1 Bios Spec Version - 0.9 Bus: 0, Dev: 28, Func: 4 Actual Expected --------------------------------------------------------------------------------- 4Ch LINK CAPABILITIES REGISTER E [11:10] Active State Link PM Support (APMS) 0x1 0x3 Desktop platform 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/WO Indicates what level of active state link power management is supported on the root port. Bits\tDefinition 00b\tNeither L0s nor L1 are supported 01b\tL0s Entry Supported 10b\tL1 Entry Supported 11b\tBoth L0s and L1 Entry Supported --------------------------------------------------------------------------------- 50h LINK CONTROL REGISTER W [1:0] Active State Link PM Control (APMC) 0x0 1,3 8.3.1. ASPM on DMI and the PCI Express* Root Ports Attribute: R/W Default: 0 Indicates whether DMI should enter L0s. 00 = Disabled 01 = L0s Entry Enabled 10 = Reserved 11 = L0s and L1 Entry Enabled --------------------------------------------------------------------------------- 70h Link Control 2 Register W [3:0] Target Link Speed (TLS) 0x0 0x1 Default: 0 This field sets an upper limit on Link operational speed by restricting the values advertised by the upstream component in its training sequences. 0001b: 2.5 GT/s Target Link Speed All other values reserved --------------------------------------------------------------------------------- E1h Root Port Dynamic Clock Gating Enable W [3] Shared Resource Dynamic Link Clock Gating 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource link clock domain. 0 = Disables dynamic clock gating of the shared resource link clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [2] Shared Resource Dynamic Backbone Clock Ga 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port shared resource Backbone clock domain. 0 = Disables dynamic clock gating of the shared resource Backbone clock domain. Only the value from Port 1 is used for ports 1–4. Only the value from Port 5 is used for ports 5-6. W [1] Root Port Dynamic Link Clock Gate Enable 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port link clock domain. 0 = Disables dynamic clock gating of the root port link clock domain. W [0] Root Port Dynamic Backbone Clock Gate Ena 0x0 0x1 13.15 Enabling Clock Gating Default: 0 1 = Enables dynamic clock gating on the root port Backbone clock domain. 0 = Disables dynamic clock gating of the root port Backbone clock domain. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 29, Func: 0 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 29, Func: 1 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* UHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 29, Func: 2 Actual Expected --------------------------------------------------------------------------------- C0h USB_LEGKEY—USB Legacy Keyboard/Mouse Control Register W [13] PCI Interrupt Enable (USBPIRQEN) 0x1 0x0 Attribute: RW Default: 1 Used to prevent the USB controller from generating an interrupt due to transactions on its ports. Note, when disabled, that it will probably be configured to generate an SMI using bit 4 of this register. Default to 1 for compatibility with older USB software. 0 =Disable 1 =Enable W [11] SMI Caused by Port 64 Write (TRAPBY64W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [10] SMI Caused by Port 64 Read (TRAPBY64R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [9] SMI Caused by Port 60 Write (TRAPBY60W) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Note that the A20Gate Pass-Through Logic allows specific port 64h writes to complete without setting this bit. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. W [8] SMI Caused by Port 60 Read (TRAPBY60R) 0x1 0x0 Attribute: RWC Default: 0 Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. 0 =Software clears this bit by writing a 1 to the bit location in any of the controllers. 1 =Event Occurred. ********************************************************************************* EHCI Controller EDS Spec Version - 2.0 Bios Spec Version - 0.95 Bus: 0, Dev: 29, Func: 7 Actual Expected --------------------------------------------------------------------------------- 6Ch USB EHCI Legacy Support Extended Control / Status W [31] SMI on BAR 0x1 0x0 Attribute: RWC Default: 0 Software clears this bit by writing a 1 to it. 0 = Base Address Register (BAR) not written. 1 = This bit is set to 1 when the Base Address Register (BAR) is written. --------------------------------------------------------------------------------- FCh Reserved E [16:4] Reserved 0x130 0x170 ********************************************************************************* LPC Bridge EDS Spec Version - 2.1 Bios Spec Version - 0.95 Bus: 0, Dev: 31, Func: 0 Actual Expected --------------------------------------------------------------------------------- A0h GEN_PMCON_1 - GENERAL PM CONFIGURATION 1 REGISTER E [4] SMI_LOCK 0x0 0x1 5.1.1 Security Recommendation Attribute: RW Default: 0 When this bit is set, writes to the GLB_SMI_EN bit will have no effect Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e. once set, this bit can only be cleared by PCIRST#). --------------------------------------------------------------------------------- A6h General Power Management Configuration Lock Register W [2] SLP_S4# Stretching Policy Lock-Down 0x0 0x1 Attribute: RW Default: 0 When set to 1, this bit locks down the SLP_S4# Minimum Assertion Width and SLP_S4# Assertion Stretch Enable bits in the GEN_PMCON_3 register, making them read-only. This bit becomes locked when a value of 1b is written to it. Writes of 0 to this bit are always ignored. This bit is cleared by PLTRST#. --------------------------------------------------------------------------------- DCh BIOS CONTROL REGISTER W [1] BIOS Lock Enable (BLE) 0x0 0x1 5.1.1 Security Recommendation Attribute: RWO Default: 0 0 = Setting the BIOSWE will not cause SMIs. 1 = Enables setting the BIOSWE bit to cause SMIs. Once set, this bit can only be cleared by a PCIRST# --------------------------------------------------------------------------------- Chipset Configuration Registers --------------------------------------------------------------------------------- 1Ch VIRTUAL CHANNEL 1 RESOURCE CAPABILITY REGISTER W [22:16] Maximum Time Slots (MTS) 0x0 0x12 7.1.1 Initialize Max Time Slot for VC1 Resource Attribute: R/WO Default: 0 This value is updated by platform BIOS based upon the determination of the number of time slots available in the platform. --------------------------------------------------------------------------------- 2010h DMC—DMI Miscellaneous Control Register W [19] DMI Misc. Control Field 1 0x0 0x1 This bit field is RESERVED!!! 13.15. Enabling Clock Gating Default: 0 R/W. BIOS shall always program this field as per the BIOS Specification. 0 = Disable DMI Power Savings. 1 = Enable DMI Power Savings. --------------------------------------------------------------------------------- 3410h GENERAL CONTROL AND STATUS REGISTER E [0] BIOS Interface Lock-Down (BILD) 0x0 0x1 5.1.1 Security Recommendation Attribute: RWO Default: 0 0 = Disabled. 1 = Prevents BUC.TS (offset 3414, bit 0) and GCS.BBS (offset 3410h, bits 11:10) and GCS.BBS (offset 3410h, bits 11:10) from being changed. This bit can only be written from 0 to 1 once. --------------------------------------------------------------------------------- 341Ch CLOCK GATING W [31] Legacy (LPC) Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = Legacy Dynamic Clock Gating is Disabled 1 = Legacy Dynamic Clock Gating is Enabled W [29:28] USB UHCI Dynamic Clock Gate Enable 0x0 0x3 Attribute: RW Default: 0 00 =USB UHCI Dynamic Clock Gating is Disabled 11 = USB UHCI Dynamic Clock Gating is Enabled 01 =Reserved 10 =Reserved W [27] SATA Port 3 Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 3 Dynamic Clock Gating is Disabled 1 = SATA Port 3 Dynamic Clock Gating is Enabled W [26] SATA Port 2 Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 2 Dynamic Clock Gating is Disabled 1 = SATA Port 2 Dynamic Clock Gating is Enabled W [25] SATA Port 1 Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 1 Dynamic Clock Gating is Disabled 1 = SATA Port 1 Dynamic Clock Gating is Enabled W [24] SATA Port 0 Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 0 Dynamic Clock Gating is Disabled 1 = SATA Port 0 Dynamic Clock Gating is Enabled W [22] HIgh Definition Audio Dynamic Clock Gate 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = HIgh Definition Audio Dynamic Clock Gating is Disabled 1 = HIgh Definition Audio Dynamic Clock Gating is Enabled W [19] USB EHCI Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = USB EHCI Dynamic Clock Gating is Disabled 1 = USB EHCI Dynamic Clock Gating is Enabled W [18] SATA Port 5 Dynamic Clock Gate Enable (D 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 5 Dynamic Clock Gating is Disabled 1 = SATA Port 5 Dynamic Clock Gating is Enabled W [17] SATA Port 4 Dynamic Clock Gate Enable (D 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = SATA Port 4 Dynamic Clock Gating is Disabled 1 = SATA Port 4 Dynamic Clock Gating is Enabled W [16] PCI Dynamic Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = PCI Dynamic Gating is Disabled 1 = PCI Dynamic Gating is Enabled W [4] PCI Express RX Clock Gating Enable (PRXCG 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = AFE Rx clock gating is disabled 1 = AFE Rx clock gating is enabled whenever all PCIe ports Rx are in squelch W [3] DMI and PCI Express* RX Dynamic Clock Gat 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = DMI and PCI Express root port RX Dynamic Clock Gating is Disabled 1 = DMI and PCI Express root port RX Dynamic Clock Gating is Enabled W [2] PCI Express TX Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = PCI Express root port TX Dynamic Clock Gating is Disabled 1 = PCI Express root port TX Dynamic Clock Gating is Enabled W [1] DMI TX Dynamic Clock Gate Enable 0x0 0x1 13.15. Enabling Clock Gating Attribute: RW Default: 0 0 = DMI TX Dynamic Clock Gating is Disabled 1 = DMI TX Dynamic Clock Gating is Enabled W [0] PCI Express root port Static Clock Gate E 0x0 0x1 13.15 Enabling Clock Gating Attribute: RW Default: 0 0 = PCI Express root port Static Clock Gating is Disabled 1 = PCI Express root port Static Clock Gating is Enabled --------------------------------------------------------------------------------- 3430h Reserved E [1:0] Reserved 0x1 0x2 BIOS Spec section 5.1 Attribute: RW Default: 0 BIOS must program this field to 01b. --------------------------------------------------------------------------------- 38C0h Reserved W [2:0] Reserved 0x0 0x7 13.15. Enabling Clock Gating Default: 0 --------------------------------------------------------------------------------- SPI Registers --------------------------------------------------------------------------------- A0h BIOS Base Address Configuration Register W [23:8] Bottom of System Flash 0x0 !0 Attribute: RW This field determines the bottom of the System BIOS. The ICH10 will not run programmed commands nor memory reads whose address field is less than this value. this field corresponds to bits 23:8 of the 3-byte address --------------------------------------------------------------------------------- C4h VSCC— Lower Vendor Specific Component Capabilities Register W [23] Vendor Component Lock (VCL) 0x0 0x1 Attribute: RWL 0': The lock bit is not set '1': The Vendor Component Lock bit is set. This register locks itself when set. --------------------------------------------------------------------------------- C8h VSCC— Upper Vendor Specific Component Capabilities Register W [23] Vendor Component Lock (VCL) 0x0 0x1 Attribute: RWL 0': The lock bit is not set '1': The Vendor Component Lock bit is set. This register locks itself when set. --------------------------------------------------------------------------------- Flash Descriptor\Flash Signature and Descriptor Map --------------------------------------------------------------------------------- 00h FLVALSIG - Flash Valid Signature Register W [31:0] Flash Valid Signature 0x0 0x0FF0A55A When the Flash Descriptor is not valid, the rest of the registers are not collected and are, therefore, not displayed. This field identifies the Flash Descriptor sector as valid. If the contents at this location contain 0FF0A55Ah, then the Flash Descriptor is considered valid and it will operate in Descriptor Mode, else it will operate in Non-Descriptor Mode. --------------------------------------------------------------------------------- 04h FLMAP0 - Flash Map 0 Register W [23:16] Flash Region Base Address (FRBA) 0x0 0x4 This identifies address bits [11:4] for the Region portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. For validation purposes, the recommended FRBA is: 04h W [7:0] Flash Component Base Address (FCBA) 0x0 0x1 This identifies address bits [11:4] for the Component portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. For validation purposes, the recommended FCBA is: 01h --------------------------------------------------------------------------------- 08h FLMAP1 - Flash Map 1 Register W [23:16] Flash ICH Strap Base Address (FISBA) 0x0 0x10 This identifies address bits [11:4] for the ICH Strap portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. For validation purposes, the recommended FISBA is: 10h W [7:0] Flash Master Base Address (FMBA) 0x0 0x6 This identifies address bits [11:4] for the Master portion of the Flash Descriptor. Bits [24:12] and bits [3:0] are 0. For validation purposes, the recommended FMBA is: 06h ********************************************************************************* Serial ATA Controller EDS Spec Version - 2.1 Bios Spec Version - 0.9 Bus: 0, Dev: 31, Func: 2 Actual Expected --------------------------------------------------------------------------------- 94h SATA Clock Gating Control Register E [23:9] Reserved 0x4000 0x0 Default: 0 --------------------------------------------------------------------------------- SATA Indexed Test Registers --------------------------------------------------------------------------------- 88h SIR88—SATA Indexed Registers Index E [29:27] Port 3 Gen 2 TX Initialization Field 0x0 2,4 Default: 0 Configures the SATA transmitter of port 3. 010 - Short Setting (Optional) - Only for SATA3TXP and SATA3TXN traces of 0.8 - 1.2 inches in length 100 - Internal SATA Setting (Recommended) - For all SATA3TXP and SATA3TXN trace lengths eSATA Setting - Recommended for all external SATA implementations All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 5:3 of Section 14.1.35.1.8. E [26:24] Port 2 Gen 2 TX Initialization Field 0x0 2,4 Default: 0 Configures the SATA transmitter of port 2. 010 - Short Setting (Optional) - Only for SATA3TXP and SATA3TXN traces of 0.8 - 1.2 inches in length 100 - Internal SATA Setting (Recommended) - For all SATA3TXP and SATA3TXN trace lengths eSATA Setting - Recommended for all external SATA implementations All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 2:0 of Section 14.1.35.1.8. E [21:19] Port 1 Gen 2 TX Initialization Field 0x0 2,4 Default: 0 Configures the SATA transmitter of port 1. 010 - Short Setting (Optional) - Only for SATA1TXP and SATA1TXN traces of 0.8 - 1.2 inches in length 100 - Internal SATA Setting (Recommended) - For all SATA1TXP and SATA1TXN trace lengths eSATA Setting - Recommended for all external SATA implementations Mobile Direct Connect Setting Mobile Docking Setting All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 5:3 of Section 14.1.35.1.2. E [18:16] Port 0 Gen 2 TX Initialization Field 0x0 2,4 Default: 0 Configures the SATA transmitter of port 10 010 - Short Setting (Optional) - Only for SATA0TXP and SATA0TXN traces of 0.8 - 1.2 inches in length 100 - Internal SATA Setting (Recommended) - For all SATA0TXP and SATA0TXN trace lengths eSATA Setting - Recommended for all external SATA implementations Mobile Direct Connect Setting Mobile Docking Setting All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 2:0 of Section 14.1.35.1.2. E [13:11] Port 3 Gen 1 TX Initialization Field 0x0 1,2 Default: 0 Configures the SATA transmitter of port 3. 001 - Short Setting (Optional) - Only for SATA3TXP and SATA3TXN traces of 0.8 - 1.2 inches in length 010 - Internal SATA Setting (Recommended) - For all SATA3TXP and SATA3TXN trace lengths eSATA Setting - Recommended for all external SATA implementations All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 29:27 of Section 14.1.35.1.8. E [10:8] Port 2 Gen 1 TX Initialization Field 2 0x0 1,2 Default: 0 Configures the SATA transmitter of port 2. 001 - Short Setting (Optional) - Only for SATA2TXP and SATA2TXN traces of 0.8 - 1.2 inches in length 010 - Internal SATA Setting (Recommended) - For all SATA2TXP and SATA2TXN trace lengths eSATA Setting - Recommended for all external SATA implementations All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 26:24 of Section 14.1.35.1.8. E [5:3] Port 1 Gen 1 TX Initialization Field 2: 0x0 1,2,4 Default: 0 Configures the SATA transmitter of port 1. 001 - Short Setting (Optional) - Only for SATA1TXP and SATA1TXN traces of 0.8 - 1.2 inches in length 010 - Internal SATA Setting (Recommended) - For all SATA1TXP and SATA1TXN trace lengths eSATA Setting - Recommended for all external SATA implementations 100 - Mobile Direct Connect Setting Mobile Docking Setting All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 21:19 of Section 14.1.35.1.8. E [2:0] Port 0 Gen 1 TX Initialization Field 2: 0x0 1,2,4 Default: 0 Configures the SATA transmitter of port 0. 001 - Short Setting (Optional) - Only for SATA0TXP and SATA0TXN traces of 0.8 - 1.2 inches in length 010 - Internal SATA Setting (Recommended) - For all SATA0TXP and SATA0TXN trace lengths eSATA Setting - Recommended for all external SATA implementations 100 - Mobile Direct Connect Setting Mobile Docking Setting All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 18:16 of Section 14.1.35.1.8. --------------------------------------------------------------------------------- A8h SIRA8—SATA Indexed Registers Index E [5:3] Port 5 Gen 1 TX Initialization Field 2: 0x0 1,2,4 Default: 0 Configures the SATA transmitter of port 5. 001 - Short Setting - Only for SATA5TXP and SATA5TXN traces of 0.8 - 1.2 inches in length 010 (Consumer Only) - Internal SATA Setting (Recommended) - For all SATA5TXP and SATA5TXN trace lengths 001 (Consumer Only) - eSATA Setting - Recommended for all external SATA implementations 100 (Corporate Only) - Internal SATA Setting (Recommended) - For all SATA5TXP and SATA5TXN trace lengths 100 (Corporate Only) - eSATA Setting - Recommended for all external SATA implementations All other values are Reserved. NOTE: The setting of this bit field must match the setting description in bits 21:19 of Section 14.1.35.1.15. --------------------------------------------------------------------------------- AHCI MMIO W BAR is disabled The BAR is disabled so no registers will be tested. Enable the BAR and collect a new dump file.